The present invention relates generally to semiconductor device manufacturing and, more particularly, to a strained, thin body semiconductor-on-insulator substrate and device.
Semiconductor-on-insulator (SOI) devices, such as silicon-on-insulator (also abbreviated in the art as “SOI”) devices, offer several advantages over more conventional semiconductor devices. For example, SOI devices may have lower power consumption requirements than other types of devices that perform similar tasks. SOI devices may also have lower parasitic capacitances than non-SOI devices. This translates into faster switching times for the resulting circuits. In addition, the phenomenon of latchup, which is often exhibited by complementary metal-oxide semiconductor (CMOS) devices, may be avoided when circuit devices are manufactured using SOI fabrication processes. SOI devices are also less susceptible to the adverse effects of ionizing radiation and, therefore, tend to be more reliable in applications where ionizing radiation may cause operation errors.
The gain of a MOS transistor, usually defined by the transconductance (gm), is proportional to the mobility (μ) of the majority carrier in the transistor channel. The current carrying capability, and hence the performance of an MOS transistor is proportional to the mobility of the majority carrier in the channel. The mobility of holes, which are the majority carriers in a P-channel field effect transistor (PFET), and the mobility of electrons, which are the majority carriers in an N-channel field effect transistor (NFET), may be enhanced by applying an appropriate stress to the channel. Existing stress engineering methods greatly enhance circuit performance by increasing device drive current without increasing device size and device capacitance. For example, a tensile stress liner applied to an NFET transistor induces a longitudinal stress in the channel and enhances the electron mobility, while a compressive stress liner applied to a PFET transistor induces a compressive stress in the channel and enhances the hole mobility.
There are several process integration methods for the creation of dual stress films. The underlying theme is the blanket deposition of a first stress layer type, followed by lithography to mask and protect this first stress layer type, an etch to remove the first stress layer type where it is not desired, and then deposition of the second stress layer type. The resulting enhanced carrier mobility, in turn, leads to higher drive currents and therefore higher circuit level performance.
However, as devices continue to scale with future technology nodes, conventional methods such as strain liners lose their effectiveness at tight pitches. Thus, substrate strain engineering is gaining more attention. While strained SOI substrates are available from wafer vendors, their manufacturing is not presently cost effective, as thick, relaxed silicon germanium (SiGe) epitaxy is required.